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agilent hcpl-7723 & HCPL-0723 50 mbd 2 ns pwd high speed cmos optocoupler data sheet description available in either 8-pin dip or so-8 package style respectively, the hcpl-7723 or HCPL-0723 optocoupler utilize the latest cmos ic technology to achieve out- standing speed performance of minimum 50 mbd data rate and 2 ns maximum pulse width distortion. basic building blocks of hcpl- 7723/0723 are a cmos led driver ic, a high speed led and a cmos detector ic. a cmos logic input signal controls the led driver ic, which supplies current to the led. the detector ic incorporates an integrated photodiode, a high speed transimpedance amplifier, and a voltage comparator with an output driver. functional diagram 8 7 6 1 3 shield 5 2 4 **v dd1 v i * gnd 1 v dd2 ** v o gnd 2 v i , input led1 h l off on truth table (positive logic) nc* i o led1 v o , output h l * pin 3 is the anode of the internal led and must be left unconnected for guaranteed datasheet performance. pin 7 is not connected internally. ** a 0.1 ? bypass capacitor must be connected between pins 1 and 4, and 5 and 8. caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation, which may be induced by esd. features +5 v cmos compatibility high speed: 50 mbd min. 2 ns max. pulse width distortion 22 ns max. prop. delay 16 ns max. prop. delay skew 10 kv/ s min. common mode rejection ?0 to 85 c temperature range safety and regulatory approvals (pending) ul recognized ?3750 v rms for 1 min. per ul1577 csa component acceptance notice #5 iec/en/din en 60747-5-2 ?viorm = 630 vpeak for hcpl-7723 option 060 ?viorm = 560 vpeak for HCPL-0723 option 060 applications digital fieldbus isolation: cc-link, devicenet, profibus, sds isolated a/d or d/a conversion multiplexed data transmission high speed digital input/output computer peripheral interface microprocessor system interface
2 package outline drawings hcpl-7723 8-pin dip package 9.65 ?0.25 (0.380 ?0.010) 1.78 (0.070) max. 1.19 (0.047) max. a xxxxv yyww date code 1.080 ?0.320 (0.043 ?0.013) 2.54 ?0.25 (0.100 ?0.010) 0.51 (0.020) min. 0.65 (0.025) max. 4.70 (0.185) max. 2.92 (0.115) min. dimensions in millimeters and (inches). 5 6 7 8 4 3 2 1 5?typ. 0.254 + 0.076 - 0.051 (0.010 + 0.003) - 0.002) 7.62 ?0.25 (0.300 ?0.010) 6.35 ?0.25 (0.250 ?0.010) type number *option 300 and 500 not marked. note: floating lead protrusion is 0.15 mm (6 mils) max. option 060 code* 3.56 ?0.13 (0.140 ?0.005)
3 hcpl-7723 package with gull wing surface mount option 300 HCPL-0723 small outline so-8 package 0.635 0.25 (0.025 0.010) 12 nom. 9.65 0.25 (0.380 0.010) 0.635 0.130 (0.025 0.005) 7.62 0.25 (0.300 0.010) 5 6 7 8 4 3 2 1 9.65 0.25 (0.380 0.010) 6.350 0.25 (0.250 0.010) 1.016 (0.040) 1.27 (0.050) 10.9 (0.430) 2.0 (0.080) land pattern recommendation 1.080 0.320 (0.043 0.013) 3.56 0.13 (0.140 0.005) 1.780 (0.070) max. 1.19 (0.047) max. 2.54 (0.100) bsc dimensions in millimeters (inches). lead coplanarity = 0.10 mm (0.004 inches). note: floating lead protrusion is 0.15 mm (6 mils) max. 0.254 + 0.076 - 0.051 (0.010 + 0.003) - 0.002) xxxv yww 8765 4 3 2 1 5.994 0.203 (0.236 0.008) 3.937 0.127 (0.155 0.005) 0.406 0.076 (0.016 0.003) 1.270 (0.050) bsc 5.080 0.127 (0.200 0.005) 3.175 0.127 (0.125 0.005) 1.524 (0.060) 45 x 0.432 (0.017) 0.228 0.025 (0.009 0.001) type number (last 3 digits) date code 0.305 (0.012) min. total package length (inclusive of mold flash) 5.207 0.254 (0.205 0.010) dimensions in millimeters (inches). lead coplanarity = 0.10 mm (0.004 inches) max. option number 500 not marked. note: floating lead protrusion is 0.15 mm (6 mils) max. 0.203 0.102 (0.008 0.004) 7 pin one 0 ~ 7 * * 7.49 (0.295) 1.9 (0.075) 0.64 (0.025) land pattern recommendation
4 device selection guide 8-pin dip (300 mil) small outline so-8 hcpl-7723 HCPL-0723 ordering information specify part number followed by option number (if desired) example: hcpl-7723- xxxx 060 = iec/en/din en 60747-5-2 option. 300 = gull wing surface mount option (hcpl-7723 only). 500 = tape and reel packaging option. xxxe = lead free option. no option and option 300 contain 50 units (hcpl-7723), 100 units (HCPL-0723) per tube. option 500 contain 1000 units (hcpl-7723), 1500 units (HCPL-0723) per reel. option data sheets available. contact sales representative or authorized distributor.
5 solder reflow temperature profile regulatory information the hcpl-7723/0723 have been approved by the following organizations: ul recognized under ul1577, component recognition program, file e55361. csa approved under csa component acceptance notice #5, file ca88324. iec/en/din en 60747-5-2 approved under: iec 60747-5-2:1997+a1:2002/ en 60747-5-2:2001+a1:2002/ din en 60747-5-2 (vde 0884 teil 2): 2003-01. (option 060 only) insulation and safety related specifications value parameter symbol 7723 0723 units conditions minimum external air gap l(i01) 7.1 4.9 mm measured from input terminals to output (clearance) terminals, shortest distance through air. minimum external tracking l(i02) 7.4 4.8 mm measured from input terminals to output (creepage) terminals, shortest distance path along body. minimum internal plastic gap 0.08 0.08 mm insulation thickness between emitter and (internal clearance) detector; also known as distance through insulation. tracking resistance cti 175 175 volts din iec 112/vde 0303 part 1 (comparative tracking index) isolation group iiia iiia material group (din vde 0110, 1/89, table 1) 0 time (seconds) temperature ( c) 200 100 50 150 100 200 250 300 0 30 sec. 50 sec. 30 sec. 160 c 140 c 150 c peak temp. 245 c peak temp. 240 c peak temp. 230 c soldering time 200 c preheating time 150 c, 90 + 30 sec. 2.5 c 0.5 c/sec. 3 c + 1 c/ 0.5 c tight typical loose room temperature preheating rate 3 c + 1 c/ 0.5 c/sec. reflow heating rate 2.5 c 0.5 c/sec. recommended pb-free ir profile 217 c ramp-down 6 c/sec. max. ramp-up 3 c/sec. max. 150 - 200 c 260 +0/-5 c t 25 c to peak 60 to 150 sec. 20-40 sec. time within 5 c of actual peak temperature t p t s preheat 60 to 180 sec. t l t l t smax t smin 25 t p time temperature notes: the time from 25 c to peak temperature = 8 minutes max. t smax = 200 c, t smin = 150 c
6 all agilent data sheets report the creepage and clearance inherent to the optocoupler component itself. these dimensions are needed as a starting point for the equipment designer when determining the circuit insulation requirements. however, once mounted on a printed circuit board, minimum creepage and clearance requirements must be met as specified for individual equipment standards. for creepage, the shortest distance path along the surface of a printed circuit board between the solder fillets of the input and output leads must be considered. there are recommended techniques such as grooves and ribs, which may be used on a printed circuit board to achieve desired creepage and clearances. creepage and clearance distances will also change depending on factors such as pollution degree and insulation level. iec/en/din en 60747-5-2 insulation related characteristics (option 060) hcpl-7723 HCPL-0723 description symbol option 060 option 060 units installation classification per din vde 0110/1.89, table 1 for rated mains voltage 150 v rms i-iv i-iv for rated mains voltage 300 v rms i-iv i-iii for rated mains voltage 450 v rms i-iii climatic classification 55/85/21 55/85/21 pollution degree (din vde 0110/1.89) 2 2 maximum working insulation voltage v iorm 630 560 v peak input to output test voltage, method b* v pr 1181 1050 v peak v iorm x 1.875 = v pr , 100% production test with t m = 1 sec, partial discharge < 5 pc input to output test voltage, method a* v pr 945 840 v peak v iorm x 1.5 = v pr , type and sample test, t m = 60 sec, partial discharge < 5 pc highest allowable overvoltage* v iotm 6000 4000 v peak (transient overvoltage, t ini = 10 sec) safety limiting values (maximum values allowed in the event of a failure, also see thermal derating curve, figure 11) case temperature t s 175 150 c input current i s,input 230 150 ma output power p s,output 600 600 mw insulation resistance at t s , v io = 500 v r io 10 9 10 9 ? *refer to the front of the optocoupler section of the isolation and control component designer? catalog , under product safety regulations section iec/en/din en 60747-5-2, for a detailed description. note: these optocouplers are suitable for ?afe electrical isolation?only within the safety limit data. maintenance of the safety d ata shall be ensured by means of protective circuits. note: the surface mount classification is class a in accordance with cecc 00802.
7 absolute maximum ratings parameter symbol min. max. units storage temperature t s ?5 125 c ambient operating temperature [1] t a ?0 85 c supply voltages v dd1 , v dd2 0 6.0 volts input voltage v i ?.5 v dd1 +0.5 volts output voltage v o ?.5 v dd2 +0.5 volts average output current i o 10 ma lead solder temperature 260 c for 10 sec., 1.6 mm below seating plane solder reflow temperature profile see solder reflow temperature profile section recommended operating conditions parameter symbol min. max. units ambient operating temperature t a ?0 85 c supply voltages v dd1 , v dd2 4.5 5.5 v logic high input voltage v ih 2.0 v dd1 v logic low input voltage v il 0.0 0.8 v input signal rise and fall times t r, t f 1.0 ms electrical specifications test conditions that are not specified can be anywhere within the recommended operating range. all typical specifications are at t a = +25 c, v dd1 = v dd2 = +5 v. parameter symbol min. typ. max. units test conditions logic low input supply current [2] i dd1l 710mav i = 0 v logic high input supply current [2] i dd1h 1.8 3 ma v i = v dd1 output supply current i dd2l 12.5 17.5 ma i dd2h 12 16.5 ma input current i i ?0 10 a logic high output voltage v oh 4.4 5.0 v i o = ?0 a, v i = v ih 4.0 4.8 v i o = ? ma, v i = v ih logic low output voltage v ol 0 0.1 v i o = 20 a, v i = v il 0.5 1.0 v i o = 4 ma, v i = v il
8 switching specifications test conditions that are not specified can be anywhere within the recommended operating range. all typical specifications are at t a = +25 c, v dd1 = v dd2 = +5 v. parameter symbol min. typ. max. units test conditions propagation delay time to logic t phl 16 22 ns c l = 15 pf cmos signal levels low output [3] propagation delay time to logic t plh 16 22 ns c l = 15 pf cmos signal levels high output [3] pulse width pw 20 ns c l = 15 pf cmos signal levels maximum data rate 50 mbd c l = 15 pf cmos signal levels pulse width distortion [4] |t phl - t plh | |pwd| 1 2 ns c l = 15 pf cmos signal levels propagation delay skew [5] t psk 16 ns c l = 15 pf cmos signal levels output rise time (10% ?90%) t r 8nsc l = 15 pf cmos signal levels output fall time (90% - 10%) t f 6nsc l = 15 pf cmos signal levels common mode transient immunity |cm h | 10 15 kv/ sv cm = 1000 v , t a = 25 c, at logic high output [6] v i = v dd1, v o > 0.8 v dd2 common mode transient immunity |cm l | 10 15 kv/ sv cm = 1000 v , t a = 25 c, at logic low output [6] v i = 0 v , v o < 0.8 v
9 package characteristics all typical specifications are at t a = 25 c. parameter symbol min. typ. max. units test conditions input-output momentary ?723 v iso 3750 v rms rh 50%, t = 1 min, ?723 3750 t a = 25 c input-output resistance [7] r i-o 10 12 ? v i-o = 500 v dc input-output capacitance c i-o 0.6 pf f = 1 mhz input capacitance [10] c i 3.0 pf input ic junction-to-case ?723 jci 145 c/w thermocouple located at thermal resistance center underside of package output ic junction-to-case ?723 jco 145 c/w ?723 135 package power dissipation p pd 150 mw notes: 1. absolute maximum ambient operating temperature means the device will not be damaged if operated under these conditions. it d oes not guarantee functionality. 2. the led is on when vi is low and off when vi is high. 3. tphl propagation delay is measured from the 50% level on the falling edge of the vi signal to the 50% level of the falling e dge of the vo signal. tplh propagation delay is measured from the 50% level on the rising edge of the vi signal to the 50% level of the rising edge of the vo signal. 4. pwd is defined as |tphl - tplh|. %pwd (percent pulse width distortion) is equal to the pwd divided by pulse width. 5. tpsk is equal to the magnitude of the worst case difference in tphl and/or tplh that will be seen between units at any given temperature within the recommended operating conditions. 6. cmh is the maximum common mode voltage slew rate that can be sustained while maintaining vo > 0.8 vdd2. cml is the maximum c ommon mode voltage slew rate that can be sustained while maintaining vo < 0.8 v. the common mode voltage slew rates apply to both ris ing and falling common mode voltage edges. 7. device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together. 8. in accordance with ul1577, each HCPL-0723 is proof tested by applying an insulation test voltage 4500 vrms for 1 second (leakage detection current limit, ii-o 5 a). each hcpl-7723 is proof tested by applying an insulation test voltage 4500 vrms for 1 second (leakage detection current limit. ii-o 5 a.) 9. the input-output momentary withstand voltage is a dielectric voltage rating that should not be interpreted as an input-outpu t continuous voltage rating. for the continuous voltage rating refer to your equipment level safety specification or agilent application not e 1074 entitled ?ptocoupler input-output endurance voltage. 10. ci is the capacitance measured at pin 2 (vi). withstand voltage [7,8,9] ?723 160 thermal resistance
10 application information bypassing and pc board layout the hcpl-7723/0723 optocouplers are extremely easy to use. no external interface circuitry is required because the hcpl-7723/0723 use high-speed cmos ic technology allowing cmos logic to be connected directly to the inputs and outputs. as shown in figure 1, the only external components required for proper operation are two bypass capacitors. capacitor values figure 3. timing diagram to illustrate propagation delay, tplh and tphl. input t plh t phl output v i v o 10% 90% 90% 10% v oh v ol 0 v 50% 5 v cmos 2.5 v cmos figure 1. functional diagram. should be between 0.01 f and 0.1 f. for each capacitor, the total lead length between both ends of the capacitor and the power-supply pins should not exceed 20 mm. figure 2 illustrates the recommended printed circuit board layout for the hcpl-7723/ 0723. propagation delay, pulse-width distortion and propagation delay skew propagation delay is a figure of merit which describes how quickly a logic signal propagates through figure 2. recommended printed circuit board layout. a system as illustrated in figure 3. the propagation delay from low to high (t plh ) is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. similarly, the propagation delay from high to low (t phl ) is the amount of time required for the input signal to propagate to the output, causing the output to change from high to low. 7 5 6 8 2 3 4 1 gnd 2 c1 c2 nc v dd2 nc v o v dd1 v i hcpl-7723 or HCPL-0723 c1, c2 = 0.01 f to 0.1 f gnd 1 v dd2 c1 c2 hcpl-7723 or HCPL-0723 v o gnd 2 v dd1 v i gnd 1 c1, c2 = 0.01 f to 0.1 f
11 pulse-width distortion (pwd) is the difference between t phl and t phl and often determines the maximum data rate capability of a transmission system. pwd can be expressed in percent by dividing the pwd (in ns) by the minimum pulse width (in ns) being transmitted. typically, pwd on the order of 20-30% of the minimum pulse width is tolerable. propagation delay skew, t psk , is an important parameter to consider in parallel data applica- tions where synchronization of signals on parallel data lines is a concern. if the parallel data is being sent through a group of optocouplers, differences in propagation delays will cause the data to arrive at the outputs of the optocouplers at different times. if this difference in propagation delay is large enough it will determine the maximum rate at which parallel data can be sent through the optocouplers. propagation delay skew is defined as the difference between the minimum and maximum propagation delays, either t plh or t phl , for any given group of optocouplers which are operating under the same conditions (i.e., the same drive current, supply voltage, output load, and operating temperature). as illustrated in figure 4, if the inputs of a group of optocouplers are switched either on or off at the same time, t psk is the difference between the shortest propagation delay, either t plh or t phl , and the longest propagation delay, either t plh or t phl . as mentioned earlier, t psk can determine the maximum parallel data transmission rate. figure 5 is the timing diagram of a typical parallel data application with both the clock and data lines being sent through the optocouplers. the figure shows data and clock signals at the inputs and outputs of the optocouplers. in this case the data is assumed to be clocked off of the rising edge of the clock. propagation delay skew represents the uncertainty of where an edge might be after being sent through an optocoupler. figure 5 shows that there will be uncertainty in both the data and clock lines. it is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all of the data outputs have settled, or some of the data outputs may start to change before the clock signal has arrived. from these considerations, the absolute minimum pulse width that can be sent through optocouplers in a parallel application is twice t psk . a cautious design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem. the hcpl-7723/0723 optocouplers offer the advantage of guaranteed specifications for propagation delays, pulse-width distortion, and propagation delay skew over the recommended temperature and power supply ranges. figure 4. timing diagram to illustrate propagation delay skew, tpsk. 50% 50% t psk v i v o v i v o 2.5 v, cmos 2.5 v, cmos data inputs clock data outputs clock t psk t psk figure 5. parallel data transmission example.
www.agilent.com/semiconductors for product information and a complete list of distributors, please go to our web site. for technical assistance call: americas/canada: +1 (800) 235-0312 or (916) 788-6763 europe: +49 (0) 6441 92460 china: 10800 650 0017 hong kong: (+65) 6756 2394 india, australia, new zealand: (+65) 6755 1939 japan: (+81 3) 3335-8152 (domestic/interna- tional), or 0120-61-1280 (domestic only) korea: (+65) 6755 1989 singapore, malaysia, vietnam, thailand, philippines, indonesia: (+65) 6755 2044 taiwan: (+65) 6755 1843 data subject to change. copyright ? 2005 agilent technologies, inc. obsoletes 5989-0833en march 1, 2005 5989-2136en

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